The present invention relates to dynamic synchronous binary counters with ratio-type stages of identical design which are implemented with insulated-gate field-effect transistors and operated with two clock signals, cf. the preambles of the two independent claims 1 and 2. The features contained therein are known from German Offenlegungsschrift No. DE 28 46 957 A1, FIG. 2. Although this is not specifically indicated there, it can be assumed that the clock signals used there are the known nonoverlapping clock signals of the ratio-type two-phase design of integrated circuits implemented with insulated-gate field-effect transistors; see, for example, the journal "The Electronic Engineer", March 1970, pages 56 to 61.
In the prior art arrangement disclosed in the above Offenlegungsschrift, the two clock signals are used only in the least significant stage, while in the respective following stages, the first clock signal is the output signal of the carry transfer transistor. Thus, as the number of stages increases, the frequency of the second clock signal controlling the respective stage decreases in accordance with the associated power of two. From this it follows that the possible total number of stages is limited, for a minimum clock-signal frequency is necessary for dynamic operation. The inventors consider that, in the present state of the art, only about eight-stage synchronous binary counters are likely to be realizable with the known arrangement.